Synopsys Design Compiler Tutorial |top|

# Example .synopsys_dc.setup set target_library "saed90nm_typ.db" set link_library "saed90nm_typ.db" "dw_foundation.sldb" set symbol_library "saed90nm.sdb" set search_path [list . "../rtl" "../libs" $search_path]

Start your script:

Your job as the designer is to guide this process using . synopsys design compiler tutorial

write -format verilog -output results/counter_netlist.v write_sdc results/counter.sdc

Run:

# Check for unmapped logic (Did everything turn into gates?) check_design

# Set the target technology set target_library tcbn25lv.db # Example

read_verilog rtl/top.v rtl/alu.v rtl/ctrl.v current_design top link check_design

report_area -hierarchy